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GD5F4GQ4UAYIG SPI(串行外设接口)的NAND闪存

资料大小: 795KB 所需积分: 0 下载次数: 用户评论: 0条评论,查看 上传日期: 2017-10-09 上 传 者: mikeneko他上传的所有资料

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标签:SPI(239)闪存(311)
GD5F4GQ4UAYIG
  SPI (Serial Peripheral Interface) NAND Flash provides an ultra cost-effecTIve while high density non-volaTIle memory storage soluTIon for embedded systems, based on an industry-standard NAND Flash memory core. It is an attracTIve alternative to SPI-NOR and standard parallel NAND Flash, with advanced features: • Total pin count is 8, including VCC and GND • Density range from 256Mbit to 8Gbit • Superior write performance and cost per bit over SPI-NOR • Significant low cost than parallel NAND This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the same pinout from one density to another. The command sets resemble common SPI-NOR command sets, modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash memory, with specified designed features to ease host management: • User-selectable internal ECC. ECC code is generated internally during a page program operation. When a page is read to the cache register, the ECC code is detect and correct the errors when necessary. The 64-bytes spare area is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status. • Assistant Block Management. With corresponding options set, the device can prohibit the Bad Block from being erased. This option features favor the block management convenience and enhance the performance. • Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. • Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power on, then host can directly read data from cache for easy boot. Also the data is promised correctly by internal ECC. It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the status of device operation.
GD5F4GQ4UAYIG SPI(串行外设接口)的NAND闪存

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